1. Field of the Invention
This invention relates to a semiconductor memory device, a semiconductor device having a semiconductor memory device and logic circuit formed in one chip or a semiconductor device such as a system on chip (SoC) and more particularly to a semiconductor device having an ECC circuit to correct an error in data read out from a semiconductor memory device.
2. Description of the Related Art
Miniaturization of elements with the development of the semiconductor device technology causes a reduction in the memory node capacitance of each memory cell in a semiconductor memory device and a soft error tends to become a serious problem.
Therefore, as the countermeasure against the soft error, an error correcting code (ECC) circuit is provided in the chip (for example, refer to K. Arimoto et al., “A Speed-Enhanced DRAM Array Architecture with Embedded ECC,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 1, FEBRUARY 1990, pp. 11-17). In a semiconductor memory device having the ECC circuit, code bits for checking are stored in addition to normal data bits and the presence or absence of an error in the data bits is detected based on the value of the code bits. Further, the bit position in which the error has occurred is detected by use of the ECC circuit, the error is corrected and error-corrected data is output. In the ECC circuit, the number of error bits of memory cells selected by the same word which can be corrected is determined according to a code used. Generally, a single error correction-double error detection (SEC-DED) code which can be used to make one-bit error correction or 2-bit error detection in addition to one-bit error correction is widely used.
In the conventional semiconductor memory device having the ECC circuit, the number of code bits required for correcting a one-bit error is different depending on the number of data bits. For example, a 7-bit code is required for correcting a one-bit error in 32-bit data. Therefore, memory cells for the code bits of seven bits in addition to data bits of 32 bits are required and the total memory capacity which is approximately 1.22 times the original memory capacity is required.
In order to suppress an increase in the memory capacity due to use of the code bits, a method for applying the ECC circuit to cope with a larger number of data bits in the semiconductor memory device is proposed. For example, an ECC circuit is used to cope with 128-bit data in the internal portion and desired 32-bit data is selected from corrected 128-bit data by use of a multiplexer and output. In this case, since a code of nine bits can be used to cope with 128-bit data, the total memory capacity can be suppressed to approximately 1.07 times the original memory capacity.
However, with the above configuration, there occurs a problem that the operation becomes complicated and the operation speed is lowered. This is specifically explained below. In the data read operation, first, “128 bits (data)+9 bits (code)” are read out and then an error in the data (128 bits) is corrected by use of the ECC circuit. After this, data of required 32 bits among the 128-bit data is multiplexed and output.
In the write operation, it is necessary to first read out all of the 128-bit data before 32-bit data is written. This is because the code bit cannot be calculated if all of the 128-bit data is not arranged and it is necessary to read out 96-bit data other than the 32-bit data which is to be written.
Therefore, when a write command is issued, it is required for the semiconductor memory device to perform two operations of the read operation and write operation. As a result, there occurs a problem that the operation speed is lowered to approximately half in comparison with a case of the normal write operation.